Then timing analyzer and power analyzer integrated in ise are used to analyze the frequency character and power character 并利用ise中集成的時(shí)序分析器和功耗分析器進(jìn)行分析。
( 4 ) use visual c + + to develop one ie measuring system mainly including the data acquisition recorder , real time analyzer and frequency domain analyzer ( 4 )以visualc + +面對(duì)對(duì)象的編程語言,開發(fā)了一套ie測量系統(tǒng),主要由數(shù)據(jù)采集、實(shí)時(shí)分析和頻譜分析三部分組成。
The thesis also introduces the virtual instrument ’ s concept , system architecture , etc . the development of virtual instrument ’ s application software is discussed in detail . it includes virtual instrument software architecture ( visa ) , and virtual instrument ’ s software platforms . the thesis discusses the principle and mechanism of work of the simulation of embedded system . by comparing with the principle of traditional logical analyzer , it draw a conclusion that the virtual logical analyzer will work in synchronous way when it is used for both logical state analyzer and logical time analyzer . the thesis 論文接著探討了嵌入式仿真平臺(tái)的原理和工作機(jī)制,通過與傳統(tǒng)邏輯分析儀原理的比較,得出了嵌入式仿真平臺(tái)下邏輯分析儀無論是做定時(shí)分析,還是做狀態(tài)分析都工作在同步方式下;并重點(diǎn)剖析了探頭原理,采樣定理和毛刺,數(shù)據(jù)的建立和保持時(shí)間等邏輯分析儀的重要技術(shù)指標(biāo),得出了虛擬環(huán)境對(duì)虛擬邏輯分析儀的功能和各項(xiàng)技術(shù)指標(biāo)的影響,還提出了流水線狀態(tài)表的思想和實(shí)現(xiàn)機(jī)制。